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| dcdc converter optimos ipol ir38163/363/165/365 1 rev 3.3 dec 1 5 , 2017 single - input voltage, 15a & 30a buck regulator s with svid features ? internal ldo allows single 16 v operation ? output voltage range: 0. 5 v to 0. 875 * p vin ? 0.5% accurate reference voltage ? intel vr12.5 (rev 1.5) ; vr13 (rev 1.0) and svid (rev 1.7) compliant ? enhanced line/load regulation with feedforward ? frequency programmable by pmbus up to 1.5 mhz ? enable input with voltage monitoring capability ? remote sense amplifier with true differential voltage sensing ? fast mode i2c and 400 khz pmbus interface for programming, sequencing and margining output voltage, and for monitoring input voltage, output voltage, output current and temperature. ? pmbus configurable fault thresholds for input uvlo, output ovp, ocp and thermal shutdown. ? thermally compensated pulse - by - pulse current limit and hiccup mode over current protection ? dedicated output voltage sensing for power good indication and overvoltage protection which remains active even when enable is low. ? enhanced pre - bias start up ? integrated mosfet drivers and bootstrap diode ? operating junction temp: - 40 o c ir38163/363/165/365 2 rev 3.3 dec 1 5 , 2017 pin diagram figure 2 : ir38163 /363 /165/365 package top view 5mm x 7 mm pqfn *ir38165 and ir38365 do not support pmbus and pin 17 is a no connect (nc) ordering information package tape and reel qty part number description pqfn 4000 ir38163mtrpbf 30a buck regulator with svid and pmbus for vccio pqfn 4000 ir38363mtrpbf 15a buck regulator with svid and pmbus for vmcp pqfn 4000 IR38165MTRPBF 30a buck regulator with svid for vccio pqfn 4000 ir38365mtrpbf 15a buck regulator with svid for vmcp ir38163/363/165/365 3 rev 3.3 dec 1 5 , 2017 functional block dia gram figure 3 : simplified block diagram for ir38163/ir38363 /ir38165/ir38365 gate drive logic + control and fault logic vcc fb vin boot sw pgnd pvin enable e / a - + vldoref ldo vcc vcc current sense uvcc hdin lgnd comp ldin uvcc vdac 2 hdrv ldrv temperature sense svid interface , smbus interface , logic , command and status registers sda scl salert / nc vsns rs + rs - rso fault control oc _ fault ov _ fault fault fault vsns ot _ fault uven pgood _ offset _ dac uvp 1 v 8 p 1 v 8 addr - fccm p 1 v 8 ldo vcc isense pvin ot _ fault oc _ fault tmon pgood uv _ en vin _ off _ dac vin _ on _ dac iout _ oc _ fault _ dac vin _ uv _ dac vin _ ov _ dac vout _ ov _ offset _ dac vdac 2 vdac 1 ovin uvin oc fault off vo ut o v sv _ clk sv _ dio sv _ alert ir38163/363/165/365 4 rev 3.3 dec 1 5 , 2017 pin descriptions pin # pin name pin description 1 pvin input voltage for power stage. bypass capacitors between pvin and pgnd should be connected very close to this pin and pgnd. typical applications use four 22 uf input capacitors and a low esr, low esl 0.1uf decoupling capacitor in a 0603/0402 case size. a 3.3nf capacitor may also be used in parallel with these input capacitors to reduce ringing on the sw node. 2 boot supply voltage for high side driver . a 0 .1uf capacitor should be connected from this pin to the sw pin. it is recommended to provide a placement for a 0 ohm resistor in series with the capacitor. for applications in which pvin>14v, a 1 ohm resistor is required in series with boot capacitor. 3 e nable enable pin to turn on and off the ic 4 addr a resistor should be connected from this pin to lgnd to s et the pmbus address offset for the device. it is recommended to provide a placement for a 10 nf capacitor in parallel with the offset resistor. 5 vsns sense pin for ovp and pgood . typically connected to a local vout capacitor at the output of the inductor. 6 fb inverting input to the error amplifier. this pin is connected directly to the output of the regulator or to the output of the remote sense amplifier, via resistor divider to set the output voltage and provide feedback to the error amplifier. 7 comp output of error amplifier. an external resistor and capacitor network is typically connected from this pin to fb to provide loop compensation. 8 rso remote s ense a mplifier o utput . when the remote sense amplifier is used, this is connected to the feedback compensation network 9 rs - remote sense amplifier input. connect to ground at the load. 10 rs+ remote sense amplifier input. connect to output at the load. 11 pgood power good status pin. output is open drain. connect a pull up resistor from this pin to vcc. if the power good voltage before vcc uvlo needs to be limited to < 500 mv, use a 49.9k pullup, otherwise a 4.99k pullup will suffice. 12, 25 pgnd power ground. this pin should be connected to the systems power ground plane. bypass 13 lgnd signal ground for internal reference and control circuitry. this should be connected to the pgnd plane at a quiet location using a single point connection. 14 sv_clk svid clk line . this is pulled up to vddio/vccio voltage . it is recommended to provide a placement for a 0603 resistor between the pin and the pullup resistor 15 sv_dio svid data line . this is pulled up to vddio/vccio voltage. it is recommended to provide a placement for a 0603 resistor between the pin and the pullup resistor 16 sv_alert svid alert line . this is pulled up to vddio/vccio voltage through a resistor. 17 salert# /nc smbus alert line ; open drain smbalert# pin. this should be pulled up to 3 .3 v - 5v with a 1k - 5k resistor . for ir38165 and ir38365, this a no connect pin. 18 sda smbus data serial input/output line . this should be pulled up to 3.3v - 5v with a 1k - 5k resistor ir38163/363/165/365 5 rev 3.3 dec 1 5 , 2017 pin # pin name pin description 19 scl smbus clock line . this should be pulled up to 3.3v - 5v with a 1k - 5k resistor 20 p1v8 this is the supply for the digital circuits; bypass with a 10 uf capacitor to pgnd . a 2.2uf capacitor is valid however a 10uf capacitor is recommended . 21 vin input voltage for ldo. a 1 uf capacitor is placed from this pin to pgnd. if the internal bias ldo is us ed, tie this pin to pvin. if an external bias voltage (typ ically 5v) is available for vcc, tie the vin pin to vcc. 22 vcc bias voltage for ic and driver section, output of ldo. add 10 uf bypass cap from this pin to pgnd. 23,26 nc nc 24 sw switch node. this pin is connected to the output inductor. dcdc converter optimos ipol ir38163 6 rev 3.3 dec 1 5 , 2017 25 a single - input voltage, synchronous buck regulator with pmbus interface absolute maximum rat ings stresses beyond th e se listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other cond itions beyond those indicated in the operational sections of the specifications are not implied. pvin, vin - 0.3v to 25v vcc - 0.3v to 6v p1v8 - 0.3v to 2 v sw - 0.3v to 25v (dc), - 4v to 25v (ac, 100ns) boot - 0.3v to 31 v boot to sw - 0.3v to 6v (dc) (note 1) , - 0.3v to 6.5v (ac, 100ns) p gd, other input/output pins - 0.3v to 6v (note 1) pgnd to gnd, rs - to gnd - 0.3v to + 0.3v thermal information junction to ambient thermal resistance ? ja 1 1 . 1 c/w (note 2) junction to c ase t op thermal resistance jc (top) 1 8 . 9 c/w (note 3) junction to pcb thermal resistance ? j b 4 . 16 c/w (note 4) junction to c ase top parameter j t (top) 0. 32 c/w (note 2) storage temperature range - 55c to 150c junction temperature range - 40c to 150c (voltages referenced to gnd unless otherwise specified) note 1: must not exceed 6v. note 2: value obtained via thermal simulation under natural convention on a vccio demo board. 10 layer, 7 x 5.5x0.072 pcb with 1.5 oz copper at the top and bottom layer. inner layers 2, 3, 8 and 9 have 1 oz copper and layers 4,5,6,7 have 2 oz copper. ta = 25c was used for the simulation. note 3 : pcb from note 2 and package is considered in thermal simulation with ta=25 ? c. pin 1 2 is considered. note 4 : only package is considered. simulation is used with a cold plate that fixes top of package at ta=25 ? c. ir38163/363/165/365 7 rev 3.3 dec 1 5 , 2017 electrical specifica tions recommended operatin g conditions symbol definition min max units pvin input bus voltage 1.5 16 * v vin ldo supply voltage 5.3 16 vcc ldo output/bias supply voltage 4.5 5.5 boot to sw high side driver gate voltage 4.5 5.5 vo output voltage 0. 5 0.875*pv in i o output current 0 30 a fs switching frequency 15 0 1500 khz t j junction temperature - 40 125 c * sw node must not exceed 25v parameter symbol conditions min typ max unit mosfet r ds(on) top switch rds(on)_top v boot C v sw = 5v, i d = 30 a, tj = 25c 2.2 m? bottom switch rds(on)_bot vcc =5v, i d = 30 a, tj = 25c 0.78 reference voltage accuracy 0 0 c ir38163/363/165/365 9 rev 3.3 dec 1 5 , 2017 parameter symbol conditions min typ max unit unity gain bandwidth bw_rs note 2 3 6.4 mhz dc gain gain_rs note 2 110 db offset voltage offset_rs 0.5v ir38163/363/165/365 11 rev 3.3 dec 1 5 , 2017 parameter symbol conditions min typ max unit bus speed 1 100 400 khz iout & vout filter 78 hz iout & vout update rate 31.2 5 khz vin & temperature filter 78 hz vin & temperature update rate 31.2 5 khz output voltage reporting resolution n vout note 2 1/256 v lowest reported vout vomon_low vsns=0v 0 v highest reported vout vomon_high vout_scale_loop=1, vsns=3.3v 3.3 v vout_scale_loop=0.5, vsns=3.3v 6.6 v vout_scale_loop=0.25, vsns=3.3v 13.2 v vout_scale_loop=0.125 , vsns=3.3v 26.4 v vout reporting accuracy 0 0 c to 85 0 c, 4.5v ir38163/363/165/365 14 rev 3.3 dec 1 5 , 2017 t ypical application d iagram s figure 4 : using the internal ldo, vo < 2.555v figure 5 : using the internal ldo, vo > 2.555v boot vcc / ldo _ out fb comp sw vo pgood pgood 5 . 5 v < vin < 16 v pvin vin enable vsns rs + rso rs - addr scl sda salert pgnd lgnd sv _ dio p 1 v 8 sv _ clk sv _ alert i 2 c / pmbus lines ; pull up to 3 . 3 v cpu serial bus placeholder for capacitor optional placeholder for boot resistor . default should be 0 ohm for pvin > 14 v , a 1 ohm resistor is required vo pgood 5 . 5 v < vin < 16 v addr boot vcc / ldo _ out fb comp sw pgood pvin vin enable vsns rs + rso rs - addr scl sda salert pgnd lgnd sv _ dio p 1 v 8 sv _ clk sv _ alert optional placeholder for boot resistor . default should be 0 ohm i 2 c / pmbus lines ; pull up to 3 . 3 / 5 v cpu serial bus placeholder for capacitor for applications in which pvin > 14 v , a 1 ohm resistor is required in series with the boot capacitor . r 2 recommend r 2 = 499 ohm ir38163/363/165/365 15 rev 3.3 dec 1 5 , 2017 t ypical application diagram s figure 6 : using external vcc, vo<2.555v figure 7 : single 5v application, vo<2.555v vo pgood 1 . 5 v < pvin < 16 v vcc = 5 v boot vcc / ldo _ out fb comp sw pgood pvin vin enable vsns rs + rso rs - addr scl sda salert pgnd lgnd sv _ dio p 1 v 8 sv _ clk sv _ alert optional placeholder for boot resistor . default should be 0 ohm for pvin > 14 v , a 1 ohm resistor is required i 2 c / pmbus lines ; pull up to 3 . 3 / 5 v cpu serial bus placeholder for capacitor vo pgood pvin = vin = vcc = 5 v boot vcc / ldo _ out fb comp sw pgood pvin vin enable vsns rs + rso rs - addr scl sda pgnd lgnd sv _ dio p 1 v 8 sv _ clk sv _ alert optional placeholder for boot resistor . default should be 0 ohm i 2 c / pmbus lines ; pull up to 3 . 3 / 5 v placeholder for capacitor ir38163/363/165/365 16 rev 3.3 dec 1 5 , 2017 typical operating ch aracteristics ( - 40c to +125c) ir38163/363/165/365 17 rev 3.3 dec 1 5 , 2017 typical operating ch aracteristics ( - 40c to +125c) ir38163/363/165/365 18 rev 3.3 dec 1 5 , 2017 typical operating characteristics ( - 40c to +125c) ir38163/363/165/365 19 rev 3.3 dec 1 5 , 2017 typical operating ch aracteristics ( - 40c to +125c) ir38163/363/165/365 20 rev 3.3 dec 1 5 , 2017 iout reporting curve s (svid) svid readings with typical reporting gain svid readings with minimum reporting gain svid readings with maximum reporting gain the mean, min and max within each plot represent the variability in the svid reading on a single part, due to noise. the table below provides a summary of measurement gain and offset taken on a statistically significant sample of parts. gain offset avera ge 0.954 0. 137 standard deviation 0.019 0. 257 min 0.919 - 0.465 max 1.009 0.95 ir38163/363/165/365 21 rev 3.3 dec 1 5 , 2017 typical efficiency a nd power loss curves pvin = vin = 12v, vcc = 5v , io=0 - 30 a, fs= 600khz, room temperature, no air flow. note that the losses of the inductor, input and output capacitors are also considered in the efficiency and power loss curves. the table below shows the indicator used for each of the output voltages in the efficien cy measurement. vout (v) lout (uh) p/n dcr (m) 0.8 0.15 hcb1 3 8380d - 151 (delta) 0.15 1 0.15 hcb138380d - 151 (delta) 0.15 1.2 0.15 hcb138380d - 151 (delta) 0.15 1.5 0.15 hcb138380d - 151 (delta) 0.15 1.8 0.15 hcb138380d - 101 (delta) 0.15 3.3 0.32 fp1308r3 - r32 - r (cooper) 0.32 5 0.32 fp1308r3 - r32 - r (cooper) 0.32 ir38163/363/165/365 22 rev 3.3 dec 1 5 , 2017 typical efficiency a nd power loss curves pvin = vin = 12v, internal ldo, io=0 - 30a, fs= 600khz, room temperature, no air flow. note that the losses of the inductor, input and output capacitors are also considered in the efficiency and power loss curves. the table below shows the indicator used f or each of the output voltages in the efficiency measurement. vout (v) lout (uh) p/n dcr (m) 0.8 0.15 hcb178380d - 151 (delta) 0.15 1 0.15 hcb138380d - 151 (delta) 0.15 1.2 0.15 hcb138380d - 151 (delta) 0.15 1.5 0.15 hcb138380d - 151 (delta) 0.15 1.8 0.15 hcb138380d - 101 (delta) 0.15 3.3 0.32 fp1308r3 - r32 - r (cooper) 0.32 5 0.32 fp1308r3 - r32 - r (cooper) 0.32 ir38163/363/165/365 23 rev 3.3 dec 1 5 , 2017 typical efficiency a nd power loss curves pvin = vin = vcc = 5v, io=0 - 30 a, fs= 600khz, room temperature, no air flow. note that the losses of the inductor, input and output capacitors are also considered in the efficiency and power loss curves. the table below shows the indicator used for each of the output voltages in the e fficiency measurement. vout (v) lout (uh) p/n dcr (m) 0.8 0.1 hcb138380d - 101 (delta) 0.15 1 0.1 hcb138380d - 101 (delta) 0.15 1.2 0.15 hcb13 8380d - 10 1 (delta) 0.15 1.5 0.15 hcb138380d - 151 (delta) 0.15 1.8 0.15 hcb138380d - 151 (delta) 0.15 ir38163/363/165/365 24 rev 3.3 dec 1 5 , 2017 theory of operation description the ir38 163 and ir38165 are 30a rated synchronous buck converters that support pmbus and i2c digital interfaces respectively. the ir38363 and ir38365 are the corresponding 15a rated versions . all the four devices in this family of optimos ipol devices are intel svid compliant and can support vr12.5 as well as vr13. they use an externally compensa ted fast, analog, pwm voltage mode control scheme to provide good noise immunity as well as fast dynamic response in a wide variety of applications. at the same time, the digital communication interface s allow complete configurability of output setting and fault functions, as well as telemetry. the switching frequency is programmable from 1 50 khz to 1.5 mhz and provides the capability of optimizing the design in terms of size and performance. it is recommended to operate at 500 khz or higher. these device s provide precisely regulated output voltage s from 0.5v to 0.8 75 * pvin programmed via two external resistors or through the communication interfaces . the y operate with an internal bias supply (ldo) , typically 5.2v. this allows operation with a single supply . the output of this ldo is brought out at the vcc pin and m ust be bypassed to the system power ground with a 10 uf decoupling capacitor. the vcc pin may also be connected to the vin pin, and an external vcc supply between 4.5v and 5.5v may be used, allowi ng an extended operating bus voltage (pvin) range from 1. 5 v to 16 v . the device utilizes the on - resistance of the low side mosfet (sync hronous mosfet ) as current sense element. this method enhances the converters efficiency and reduces cost by eliminating the need for external current sense resistor. these devices includes two low r ds(on) mosfets using infineons optimos technology. these are specifically designed for low duty cycle, high efficiency applications. device power - up and initializatio n during the power - up sequence, when vin is brought up, the internal ldo converts it to a regulated 5.2v at vcc. there is another ldo which further converts this down to 1.8v to supply the internal digital circuitry. an under - voltage lockout circuit monitors the vo ltage of v cc pin and the p1v8 pin, and holds the power - on - reset (por) low until these voltages exceed their thresholds and the internal 48 mhz oscillator is stable. when the device comes out of reset, it initializes a multiple times programmable (mtp ) memo ry load cycle, where the contents of the mtp are loaded into the working registers. once the registers are loaded from mtp, the designer can use pmbus commands to re - configure the various parameters to suit the specific vr design requirements if desired, i rrespective of the status of enable. the typical default configuration utilizes the internal ldo to supply the vcc rail when pvin is brought up . for this configuration power conversion is enabled only when the enable pin voltage exceeds its under voltag e threshold, the pvin bus voltage exceeds its under voltage threshold, the contents of the mtp have been fully loaded into the working registers and the device address has been read. the initialization sequence is shown in figure 8 . another common default configuration uses an external power supply for the vcc rail. while in this configuration it is recommended to ensure the vcc rail reaches its target voltage prior the enable signal goes high. a dditional options are available to enable the device powe r conversion through software and these options may be configured to override the default by using the i2c interface or pmbus. f or further details see the un0075 ir3816x _ir3826x_ir3836x_ pmbus commandset user note . ir38163/363/165/365 25 rev 3.3 dec 1 5 , 2017 figure 8 : initialization sequence showing pvin, vin, vcc, 1.8v, enable and vout signals as well as the internal logic signals i2c and pmbus commun ication all the devices in this family have two 7 - bit registers that are used to set the bas e i2c address and base pmbus address of the device, as shown below in table 1 . table 1 : registers used to set device base address register description i2c_address[6:0] the chip i2c address. an address of 0 will disable i2c communication . note that disabling i2c does not disable pmbus. pmbus_address[6:0] the chip pmbus address. an address of 0 will disable pmbus communication. note that disabling pmbus does not disable i 2c. in addition, a resistor may be connected between the addr and lgnd pins to set an offset from the default preconfigured i2c address (0x10) /pmbus address (0x40) in the mtp. up to 16 different offsets can be set, allowing 16 devices with unique addresses in a single system. this offset, and hence, the device address, is read by the internal 10 bit adc during the initialization sequence. table 2 below provides the resistor values needed to set the 16 offsets from the base address. table 2 : address offset vs. external resistor( r addr ) addr resistor (ohm) address offset 499 +0 p v i n = v i n v c c p 1 v 8 u v o k c l k r d y p o r i n i t i a l i z a t i o n d o n e e n a b l e v o u t ir38163/363/165/365 26 rev 3.3 dec 1 5 , 2017 1050 +1 1540 +2 2050 +3 2610 +4 3240 +5 3830 +6 4530 +7 5230 +8 6040 +9 6980 +10 7870 +11 8870 +12 9760 +13 10700 +14 > 11800 +15 the device will then respond to i2c/pmbus commands sent to this address. there is also a register bit i2c_ disable_ addr_ offset that may be set in order to instruct the device to ignore the resistor offset for both i2c and pmbus . if this bit is set, the devi ce will always respond to commands sent to the base address. modes for setting ou tput voltages these devices provide a configuration bit that allows the user to choose between pmbus and vid modes. when this bit is set, the output voltage will ramp to the c onfigured boot voltage and subsequently, respond to voltage set commands issued by the cpu on the serial vid (svid) interface. the vid tables for 5mv and 10mv vid steps are shown in the tables below. a vid code of 0 corresponds to 0v as well as the regulator shutdown code in svid mode. vboot which is utilized in the svid mode should never be set to 0 v as this will shutdown the regulator. when this bit is zero, the regulation is determined by the outpu t voltage set by the pmbus commands (for the ir38163 and ir38363) or by the corresponding mtp registers (for the ir38165 and ir38365). it should be noted that irrespective of the mode used to set the output voltage, telemetry information always remains ava ilable on both the communications busses. ir38163/363/165/365 27 rev 3.3 dec 1 5 , 2017 table 3 : intel 5mv vid table vid (hex) voltage (v) vid (hex) voltage (v) vid (hex) voltage (v) vid (hex) voltage (v) vid (hex) voltage (v) ff 1.52 c5 1.23 91 0.97 57 0.68 2f 0.48 fe 1.515 c4 1.225 90 0.965 56 0.675 2e 0.475 fd 1.51 c3 1.22 8f 0.96 55 0.67 2d 0.47 fc 1.505 c2 1.215 8e 0.955 54 0.665 2c 0.465 fb 1.5 c1 1.21 8d 0.95 53 0.66 2b 0.46 fa 1.495 c0 1.205 8c 0.945 52 0.655 2a 0.455 f9 1.49 bf 1.2 8b 0.94 51 0.65 29 0.45 f8 1.485 be 1.195 8a 0.935 50 0.645 28 0.445 f7 1.48 bd 1.19 89 0.93 4f 0.64 27 0.44 f6 1.475 bc 1.185 88 0.925 4e 0.635 26 0.435 f5 1.47 bb 1.18 87 0.92 4d 0.63 25 0.43 f4 1.465 ba 1.175 86 0.915 4c 0.625 24 0.425 f3 1.46 b9 1.17 85 0.91 4b 0.62 23 0.42 f2 1.455 b8 1.165 84 0.905 4a 0.615 22 0.415 f1 1.45 b7 1.16 83 0.9 49 0.61 21 0.41 f0 1.445 b6 1.155 82 0.895 48 0.605 20 0.405 ef 1.44 bb 1.18 81 0.89 47 0.6 1f 0.4 ee 1.435 ba 1.175 80 0.885 58 0.685 1e n/a ed 1.43 b9 1.17 7f 0.88 57 0.68 1d n/a ec 1.425 b8 1.165 7e 0.875 56 0.675 1c n/a eb 1.42 b7 1.16 7d 0.87 55 0.67 1b n/a ea 1.415 b6 1.155 7c 0.865 54 0.665 1a n/a e9 1.41 b5 1.15 7b 0.86 53 0.66 19 n/a e8 1.405 b4 1.145 7a 0.855 52 0.655 18 n/a e7 1.4 b3 1.14 79 0.85 51 0.65 17 n/a e6 1.395 b2 1.135 78 0.845 50 0.645 16 n/a e5 1.39 b1 1.13 77 0.84 4f 0.64 15 n/a e4 1.385 b0 1.125 76 0.835 4e 0.635 14 n/a e3 1.38 af 1.12 75 0.83 4d 0.63 13 n/a e2 1.375 ae 1.115 74 0.825 4c 0.625 12 n/a e1 1.37 ad 1.11 73 0.82 4b 0.62 11 n/a e0 1.365 ac 1.105 72 0.815 4a 0.615 10 n/a df 1.36 ab 1.1 71 0.81 49 0.61 f n/a de 1.355 aa 1.095 70 0.805 48 0.605 e n/a dd 1.35 a9 1.09 6f 0.8 47 0.6 d n/a dc 1.345 a8 1.085 6e 0.795 46 0.595 c n/a db 1.34 a7 1.08 6d 0.79 45 0.59 b n/a da 1.335 a6 1.075 6c 0.785 44 0.585 a n/a d9 1.33 a5 1.07 6b 0.78 43 0.58 9 n/a d8 1.325 a4 1.065 6a 0.775 42 0.575 8 n/a d7 1.32 a3 1.06 69 0.77 41 0.57 7 n/a d6 1.315 a2 1.055 68 0.765 40 0.565 6 n/a d5 1.31 a1 1.05 67 0.76 3f 0.56 5 n/a d4 1.305 a0 1.045 66 0.755 3e 0.555 4 n/a d3 1.3 9f 1.04 65 0.75 3d 0.55 3 n/a d2 1.295 9e 1.035 64 0.745 3c 0.545 2 n/a d1 1.29 9d 1.03 63 0.74 3b 0.54 1 n/a d0 1.285 9c 1.025 62 0.735 3a 0.535 0 0 cf 1.28 9b 1.02 61 0.73 39 0.53 ce 1.275 9a 1.015 60 0.725 38 0.525 cd 1.27 99 1.01 5f 0.72 37 0.52 cc 1.265 98 1.005 5e 0.715 36 0.515 cb 1.26 97 1 5d 0.71 35 0.51 ca 1.255 96 0.995 5c 0.705 34 0.505 c9 1.25 95 0.99 5b 0.7 33 0.5 c8 1.245 94 0.985 5a 0.695 32 0.495 c7 1.24 93 0.98 59 0.69 31 0.49 c6 1.235 92 0.975 58 0.685 30 0.485 ir38163/363/165/365 28 rev 3.3 dec 1 5 , 2017 table 4 : intel 10mv vid table vid (h ex ) v oltage (v) vid (h ex ) v oltage (v) vid (h ex ) v oltage (v) vid (h ex ) v oltage (v) vid (h ex ) v oltage (v) ff 3.04 c5 2.46 8b 1.88 51 1.30 17 0.72 fe 3.03 c4 2.45 8a 1.87 50 1.29 16 0.71 fd 3.02 c3 2.44 89 1.86 4f 1.28 15 0.70 fc 3.01 c2 2.43 88 1.85 4e 1.27 14 0.69 fb 3.00 c1 2.42 87 1.84 4d 1.26 13 0.68 fa 2.99 c0 2.41 86 1.83 4c 1.25 12 0.67 f9 2.98 bf 2.40 85 1.82 4b 1.24 11 0.66 f8 2.97 be 2.39 84 1.81 4a 1.23 10 0.65 f7 2.96 bd 2.38 83 1.80 49 1.22 f 0.64 f6 2.95 bc 2.37 82 1.79 48 1.21 e 0.63 f5 2.94 bb 2.36 81 1.78 47 1.20 d 0.62 f4 2.93 ba 2.35 80 1.77 46 1.19 c 0.61 f3 2.92 b9 2.34 7f 1.76 45 1.18 b 0.60 f2 2.91 b8 2.33 7e 1.75 44 1.17 a 0.59 f1 2.90 b7 2.32 7d 1.74 43 1.16 9 0.58 f0 2.89 b6 2.31 7c 1.73 42 1.15 8 0.57 ef 2.88 b5 2.30 7b 1.72 41 1.14 7 0.56 ee 2.87 b4 2.29 7a 1.71 40 1.13 6 0.55 ed 2.86 b3 2.28 79 1.70 3f 1.12 5 0.54 ec 2.85 b2 2.27 78 1.69 3e 1.11 4 0.53 eb 2.84 b1 2.26 77 1.68 3d 1.10 3 0.52 ea 2.83 b0 2.25 76 1.67 3c 1.09 2 0.51 e9 2.82 af 2.24 75 1.66 3b 1.08 1 0.50 e8 2.81 ae 2.23 74 1.65 3a 1.07 e7 2.80 ad 2.22 73 1.64 39 1.06 e6 2.79 ac 2.21 72 1.63 38 1.05 e5 2.78 ab 2.20 71 1.62 37 1.04 e4 2.77 aa 2.19 70 1.61 36 1.03 e3 2.76 a9 2.18 6f 1.60 35 1.02 e2 2.75 a8 2.17 6e 1.59 34 1.01 e1 2.74 a7 2.16 6d 1.58 33 1.00 e0 2.73 a6 2.15 6c 1.57 32 0.99 df 2.72 a5 2.14 6b 1.56 31 0.98 de 2.71 a4 2.13 6a 1.55 30 0.97 dd 2.70 a3 2.12 69 1.54 2f 0.96 dc 2.69 a2 2.11 68 1.53 2e 0.95 db 2.68 a1 2.10 67 1.52 2d 0.94 da 2.67 a0 2.09 66 1.51 2c 0.93 d9 2.66 9f 2.08 65 1.50 2b 0.92 d8 2.65 9e 2.07 64 1.49 2a 0.91 d7 2.64 9d 2.06 63 1.48 29 0.90 d6 2.63 9c 2.05 62 1.47 28 0.89 d5 2.62 9b 2.04 61 1.46 27 0.88 d4 2.61 9a 2.03 60 1.45 26 0.87 d3 2.60 99 2.02 5f 1.44 25 0.86 d2 2.59 98 2.01 5e 1.43 24 0.85 d1 2.58 97 2.00 5d 1.42 23 0.84 d0 2.57 96 1.99 5c 1.41 22 0.83 cf 2.56 95 1.98 5b 1.40 21 0.82 ce 2.55 94 1.97 5a 1.39 20 0.81 cd 2.54 93 1.96 59 1.38 1f 0.80 cc 2.53 92 1.95 58 1.37 1e 0.79 cb 2.52 91 1.94 57 1.36 1d 0.78 ca 2.51 90 1.93 56 1.35 1c 0.77 c9 2.50 8f 1.92 55 1.34 1b 0.76 c8 2.49 8e 1.91 54 1.33 1a 0.75 c7 2.48 8d 1.90 53 1.32 19 0.74 c6 2.47 8c 1.89 52 1.31 18 0.73 ir38163/363/165/365 29 rev 3.3 dec 1 5 , 2017 bus voltage uvlo i f the input to the enable pin is derived from the bus voltage by a suitably programmed resistive divider, it can be ensured that the device does not turn on until the bus voltage reaches the desired level as shown in figure 9 . only after the bus voltage reaches or exceeds this level and voltage at the enable pin exceed s its threshold (typically 0.6 v) will the device be enabled. therefore, in addition to being logic input pin to enable the converter , the enable feature, with its precise threshold, also allows the user to override the default 8 v under - voltage lockout for the bus voltage ( pvin ). th is is desirable particularly for high output voltage applications, where we might want the device to be disabled at least until pvin exceeds t he desired output voltage level . alternatively, the default 8 v pvin uvlo threshold may be reconfigured/overridden using the vin_on and vin_off pmbus commands or the corresponding registers . it should be noted that the input voltage is also fed to an adc through a 2 1:1 internal resistive divider. however, the digitized input voltage is used only for the purposes of re porting the input voltage through the read_vin pmb u s command . it has no impact on the bus voltage uvlo, input overvoltage faults and input undervoltage warnings, all of which are implemented by using analog comparators to compare the input voltage to the c orresponding thresholds programmed by the pmbus commands vin_on, vin_off, vin_ov_fault_limit and vin_uv_warn_limit respectively. the bus voltage reading as reported by read_vin has no effect on the input feedforward function either. figure 9 : normal start up, device turns on when the bus voltage reaches 10.2 a. a resistor divider is used at en pin from pvin to turn on the device at 10.2v. figure 10 : recommended startup for normal operation figure 10 shows the recommended start up sequence for the normal operation of the device , when enable is used as logic input. vcc pvin dac 2 ( reference dac ) en > 0 . 6 v 0 . 6 v en _ uvlo _ start 10 . 2 v 12 v 1 v vcc pvin = vin en > 0 . 6 v dac 2 ( reference dac ) ir38163/363/165/365 30 rev 3.3 dec 1 5 , 2017 pre - bias startup these devices can start up into a pre - cha rged output, which prevents oscillation and disturbances of the output voltage. the output starts in asynchronous fashion and keeps the synchronous mosfet (sync fet) off until the first gate signal for control mosfet (ctrl fet) is generated. figure 11 shows a typical pre - bias condition at start up. the sync fet always starts with a narrow pulse width (12.5% of a switching period) and gradually increases its duty cycle with a step of 12.5% , with 16 cycles at each step, until i t reaches the steady state value. figure 12 shows the series of 16x8 startup pulses . figure 11 : pre - bias startup figure 12 : pre - bias startup pulses soft - start ( reference dac ramp) these devices have an internal soft starting dac to control the output voltage rise and to limit the current surge at the start - up. t o ensure correct start - up, the dac sequence initiates only after power conversion is enabled when the enable pin voltage exceeds its undervoltage threshold, the pvin bus voltage exceeds its undervoltage threshold and the contents of the mtp have been fully loaded into the working registers . figure 13 shows the waveforms during soft start. it should be noted that the part may also be configured to require software enable (set through the pmbus or the corresponding mtp register ) instead of or in addition to a hardware signal at the enable pin. in pmbus mode, t he reference dac soft - start may be delayed from the time power conversion is enabled. the range for this programmable delay is 0ms to 127 ms, and the resolution is 1 ms. further, in this mode, the soft s tart time may be configured from 1ms to 127 ms with 1 ms resolution. in svid mode, the rise time is determined by the slow slew rate specified by intel, and may be programmed to one of four values: 0.625mv/us, 1.25 mv/us, 2.5 mv/us and 5 mv/us. in this mo de, the device uses 2.5 mv/us by default. it should be noted, however, that if vboot is 0, the output voltage does not ramp until the cpu issues a voltage setting command at either the fast slew rate or slow slew rate specified by the cpu . vo [ v ] [ time ] pre - bias voltage ... ... ... hdrv ... ... ... 16 end of pb ldrv 12 . 5 % 25 % 87 . 5 % 16 ... ... ... ... ir38163/363/165/365 31 rev 3.3 dec 1 5 , 2017 for more de tails on the pmbus commands ton_delay and ton_rise used to program the startup sequence, please see the un0075 ir3816x_ir3826x_ir3836x_ pmbus commandset user note. figure 13 : dac2 (vref) soft start during the startup sequence the over - current protection (ocp) and over - voltage protection (ovp) are active to protect the device against any short circuit or over voltage condition. operating frequency u sing the frequency_switch pmbus command, or the corresponding registers, the switching frequency may be programmed between 150 khz and 1.5 mhz . for best telemetry accuracy, it is recommended that the following switching frequencies be avoided: 250 khz, 300 khz, 400 khz, 500 khz, 600 khz, 750 khz, 800 khz, 1 mhz, 1.2 mhz and 1.5 mhz. instead, it is recommended to us e the f ollowing values 251 khz, 302 khz, 403 khz, 505 khz, 607 khz, 762 khz, 813 khz, 978 khz, 1171 khz and 1454 khz respectively. shutdown in the default configuration, the device can be shutdown by pulling the enable pin belo w its 0.4 v threshold. during shutd own t he hig h side and the low side drivers are turned off . by default, the device exhibits an immediate shutdown with no delay and no soft stop. alternatively, the part may be configured to allow shutdown using the operation pmbus command or the correspond ing register . it may also be configured to allow a soft or controlled turned off. in pmbus mode, if the soft - off option is used, the turn off may be delayed from the time the power conversion is disabled. the range for this programmable delay is 0ms to 127 ms, and the resolution is 1 ms. further, in this mode, the soft stop time may be configured from 1ms to 127 ms with 1 ms resolution. the programmable turn off delay only applies in pmbus mode. in pvid mod e, if the soft - stop option is used, the output voltage slews down at 0.625 mv/us. reference dac vout t 1 internal enable t 3 t 2 ton _ delay ton _ rise ir38163/363/165/365 32 rev 3.3 dec 1 5 , 2017 current sensing, tel emetry and over curr ent protection current sensing for both, telemetry as well as overcurrent protection is done by sensing the voltage across the sync f et rdson. this method enhances the converters efficiency, reduces cost by eliminating a current sense resistor and any minimizes sensitivity to layout related noise issues. a novel, patented scheme allows reconstruction of the average inductor current fr om the voltage sensed across the sync fet rdson. it should be noted here that it is this reconstructed average inductor current that is digitized by the adc and used for output current reporting as well as for overcurrent warning, the threshold for which m ay be set using the iout_oc_warn_limit command . the current is reported in 1/16a resolution using the read_iout pmbus command. for the ir38 165 and ir38365, which support i 2 c communication, but not pmbus, the current information may be read back through the 8 - bit register output_current_byt e, which reports the current in 1/4 a resolution. the o ver current (oc) fault protection circuit also uses the voltage sensed across the r ds(on) of the synchronous mosfet; however, the protection mechanism relies on a fas t comparator to compare the sensed signal to the overcurrent threshold and does not depend on the adc or reported current. the current limit scheme uses an internal temperature compensated current source that has the same temperature coefficient as the r ds (on) of the synchronous mosfet. as a result , the over - current trip threshold remains almost constant over temperature . over current protection circuit ry senses the inductor current flowing through the synchronous fet closer to the valley point. the ocp ci rcuit samples this current for 75 ns typically after the rising edge of the pwm set pulse which is an internal signal that has a width of 12.5% of the switching period. the pwm pulse that turn s on the high side fet starts at the falling edge of the pwm set pulse. this makes valley current sense more robust as current is sensed close to the bottom of the inductor downward slo pe where transient and switching noise is low . this helps to prevent false tripping due to noise and transient s . the actual dc output current limit point will be greater than the valley point by an amount equal to approximately half of the peak to peak inductor ripple current. the current limit point will be a function of the inductor value, input voltage, output voltage and the frequency of operation . on equation 1, i l imit is the value set when configuring the ocp value . the user should account f o r the inductor ripple to obtain the actual dc output current limit. ( 1 ) i ocp = dc current limit hiccup point i limit = current limit valley point i = inductor ripple current 2 i i i limit ocp ? ? ? ir38163/363/165/365 33 rev 3.3 dec 1 5 , 2017 figure 14 : timing diagram for current limit hiccup in the default configuration , if the o vercurrent detection trips the ocp comparator for a total of 8 cycles, the device goes into a hiccup mode. the hiccup is performed by de - asserting the internal enable signal to the analog and power conversion circuitry and holding it low for 20 ms . following this, the ocp signal resets and the converter recovers. after every hiccup cycle, the converter stays in this mode until the overload or short circuit is removed. this behavior is shown in figure 14 . it should be noted that o n some units, a false ocp maybe experienced during device start - up due to noise. the part will ride through this false ocp due to the pulse by pulse current limiting feature and successfully ramp to the correct output voltage . however, it is recommend ed to send a pmbus clear_faults command a fter start - up to reset the pmbus salert# to a high and to clear the pmbus status register for faults. note that t he user can override the default overcurrent threshold using the pmbus command iout_oc_fault_limit. for the ir38163/ir38165 it is recommended that the overcurrent thresh old be programmed to at least 16 a for good accuracy. for the ir38363/ir38365 a minimum threshold of 12 a is recommended. while these devices will still offer overcurrent protection for thresholds programmed lower than these recommended values, the thresholds will not be as accurate. also, using the pmbus command iout_oc_fault_response or the corresponding registers , the part may be configured to respond to an overcurrent fault in one of two ways 1) pulse by pulse current limiting for a programmed number of 8 switching cycles followed by a latched shutdown. 2) p ulse by pulse current limiting for a programmed number of 8 switching cycles followed by hiccup. this is the default explained above. the pulse - by - pulse or constant c u rrent limiting mechanism is briefly explained below . 0 i l 0 h d r v c u r r e n t l i m i t 0 l d r v . . . . . . 0 p g o o d h i c c u p t b l k _ h i c c u p 2 0 m s ir38163/363/165/365 34 rev 3.3 dec 1 5 , 2017 figure 15 : pulse by pulse current limiting for 8 cycles, followed by hiccup. in figure 15 above, with the overcurrent response set to pulse - by - pulse current limiting for 8 cycles followed by hiccup, the converter is operating at d<0.125 when the overcurrent condition occurs. in such a case, no duty cycle limiting is applied. figure 16 : constant current limiting. figure 16 depicts a case where the overcurrent condition happens when the converter is operating at d>0.5 and the overcurrent response has been set to constant current operation through pulse by pulse current limiting. in such a case, after 3 consecutive overcurrent cycles are recognized, the pulse width is dropped such that d=0.5 and then after 3 more consecutive ocp cycles, to 0.25 and then finally to 0.125 at which it keeps running until the total ocp count reaches the programmed maximum following which the part enters hiccup mode. conve rsely, when the overcurrent condition disappears, the pulse width is restored to its nominal value gradually, by a similar mechanism in reverse; every sequence of 4 consecutive cycles in which the current is below the overcurrent threshold doubles the duty cycle, so that d goes from 0.125 to 0.25, then to 0.5 and finally to its nominal value. 0 il 0 hdrv fs io ut _ oc _ fa ult _ lim it 0 0 clk ldrv internal enable ocp high 1 2 3 4 5 6 7 8 9 10 ... 11 0 il 0 hdrv fs iout _ oc _ fault _ limit 0 0 clk ldrv 20 ms internal enable ocp high 1 2 3 4 5 6 7 8 ir38163/363/165/365 35 rev 3.3 dec 1 5 , 2017 die temperature sens ing, telemetry and t hermal shutdown o n die temperature sensing is used for accurate temperature reporting and over temperature detection . the read _temeprature pmbus command reports this temperature in 1 0 c resolution. for the ir38165 and ir38365, which do not support pmbus communication, the temperature may be read back through the 8 - bit register temp _byt e, which reports the die temperature in 1 0 c resolution, offset by 40 0 c. thus, the temperature is given by temp _byte +40 0 c. the trip threshold is set by default to 1 2 5 o c. the default over temperature response of the device is to inhibit power conversion while the fault is present, followed by automa tic restart after the fault condition is cleared. hence, in the default configuration, w hen trip thresho ld is exceeded, the internal enable signal to the power conversion circuitry is de - asserted, turning off both mosfets. automatic restart is initiated wh en the sensed temperature drops within the operating range. there is a 25 o c hysteresis in the thermal shutdown threshold. the default overtemperature threshold as well as overtemperature response may be re - configured or overridden using the ot_fault_limit and ot_fault_response pmbus commands respectively. for the ir38165 and ir38365, which do not support pmbus, the corresponding registers may be used. the devices support three types of responses to an over - temperature fault: 1) ignore 2) inhibit when over tempera ture condition exists and auto - restart when over temperature condition disappears 3) latched shutdown. remote voltage sensi ng true differential remote sensing in the feedback loop is critical to high current applications where the output voltage across the l oad may differ from the output voltage measured locally across an output capacitor at the output inductor, and to applications that require die voltage sensing. the rs+ and rs - pins form the inputs to a remote sense differential amplifier with high speed, low input offset and low input bias current , which ensure accurate voltage sensing and fast transient response in such applications. the input range for the differential amplifier is limited to 1.5v below the vcc rail. therefore, for applications in which the output voltage is more than 3v, it is recommended to use local sensing, or if remote sensing is a must, then the voltage between the rs+ and rs - pins must be divided down to less than 3v using a resistive voltage divider. its recommended that the divider be placed at the input of the remote sense amplifier and that a low impedance such as 499 ? be used between the rs+ and rs - nodes . a typical schematic for this setup is shown o n figure 5 . please note, however, that this modifies the open loop transfer function and requires a change in the compensation network to optimally stabilize the loop. feed - forward feed - forward (f.f.) is an important feature, because it can keep the converter stable and preserve its load transient performance when p vin varies over a wide range . the pwm ramp amplitude (vramp) is proportionally ir38163/363/165/365 36 rev 3.3 dec 1 5 , 2017 changed with p vin to maintain p vin/vramp almost constant throughout p vin variation range (as shown in figure 17 ). thus, the control loop bandwidth and phase margin can be mai ntained constant. the f eed - forward function can also minimize impact on output voltage from fast p vin change. the feed - forward is disabled for pvin<4.7v. hence, for pvin<4.7v, a re - calculation of control loop parameters is needed for re - compensation. figure 17 : timing diagram for feed - forward (f.f.) function light load efficienc y enhancement ( aot ) these devices implement a diode emulation scheme with adaptive on time control or aot to improve light load efficiency. it is based on a cot (constant on time) control scheme with some novel advancements that make the on - time during diode emulation adaptive and dependent upon the pulse width in constant frequency operation. this allows the scheme to be com bined with a pwm scheme, while providing relatively smooth transition between the two modes of operation. in other words, the switching regulator can operate in aot mode at light loads and automatically switch to pwm at medium and heavy loads and vice vers a. therefore, the regulator will benefit from the high efficiency of the aot mode at light loads, and from the constant frequency and fast transient response of the pwm at medium to heavy loads. in pmbus mode, a mfr_specific pmbus command (mfr_fccm ) can be used to enable aot ope ration at light load for the ir38163 and ir38363. for the ir38165 and ir38365, the corresponding mtp register bit mfr_fccm must be set to 0 to allow aot operation. in svid mode, there are two ways in which aot operation may be enable d: a) auto - ps: set the mfr_fccm bit to 0. b) ps commands issued by the cpu: set the mfr_fccm bit to 1. the device will then allow aot operation only if commanded to power states ps2, ps3 or ps4 by the cpu. conversely, a command to power states ps0 or ps1 or a v id command to a higher voltage will disable aot operation. if it is desired that aot operation be disabled altogether (recommended), allowing neither auto - ps nor ps commands issued by the cpu to enable aot operation, it is essential to a) the svid_ps_overrid e bit must be set to 1. b) set svid_ps_override_val[2:0] to 0. c) set the mfr_fccm bit to 1. 0 0 p v i n p w m r a m p 1 2 v r a m p o f f s e t 2 1 v 5 v 1 2 v ir38163/363/165/365 37 rev 3.3 dec 1 5 , 2017 shortly after the reference voltage has finished ramping up, an internal circuit which is called the calibration circuit starts operation. it samples the comp voltage (output of the error amplifier), digitizes it and stores it in a register. there is a dac which converts the value of this register to an analog voltage which is equal to the sampled comp voltage. at this time, the regulator is ready to enter aot mode if the load condition is appropriate. if the load is so low that the inductor current becomes negative before the next sw pulse, the operation can be switched to aot mode. the condition to enter aot is the occurrence of 8 consecutive inductor current zero cro ssings in eight consecutive switching cycles. if this happens, operation is switched to aot mode as shown in figure 18 . the inductor current is sensed using the rds_on of the sync - fet and no direct inductor current measuring is required. in aot mode, just like cot operation, pulses with constant width are generated and diode emulation is utilized. this means that a pulse is generated and ldrv is held on until the inductor current becomes zero. then both hdrv and ldrv remain off until the voltage of the sense pin comes down and reaches the reference voltage. at this moment the next pulse is generated. the sense pin is conne cted to the output voltage by a resistor divider which has the same ratio as the voltage divider which is connected to the feedback pin (fb). figure 18 : timing diagram for reduced switching frequency a nd diode emulation in light load condition ( aot mode) when the load increases beyond a certain value, the control is switched back to pwm through either of the following two mechanisms: 1) if due to the increase in load, the output voltage drops to 95% of th e reference voltage. 2) if vsense remains below the reference voltage for 3 consecutive inductor current zero - cross events it is worth mentioning that in aot mode, when vsense comes down to reference voltage level, a new pulse in generated only if the induc tor current is already zero. if at this time the inductor current (sensed on the sync - fet) is still positive, the new pulse generation is postponed till the current decays to zero. the second condition mentioned above usually happens when the load is gradu ally increased. aot is disabled during output voltage transition s . it is enabled only after reference voltage finishes its ramp (up or down) and the calibration circuit has sampled and held the new comp voltage. hdrv 0 0 ldrv 0 sw 0 il ton 0 vout ... ... ... ... ... ... ... ... 1 / fs reduced switching frequency 8 / fs delay diode emulation ir38163/363/165/365 38 rev 3.3 dec 1 5 , 2017 in general, aot operation is more jittery and noisier than fccm operation, where the switching frequency may vary from cycle to cycle, giving increased vout ripple and noisier, inconsistent telemetry . therefore, it is recommended to use fccm mode of operation as far as possible. output voltage sen sing , telemetry and faul ts for this family of devices, the voltage sense and regulation circuits are decoupled, enabling ease of testing as well as redundancy. in order to do this, the device uses the sense voltage at the dedicated vsns pin for output voltage reporting (in 1/256 v resolution, using the read_vout pmbus command) as well as for power good detection and output overvoltage protection. power good detection and output overvoltage de tection rely on fast analog comparator circuits, whereas overvoltage warnings as well as undervoltage faults and warnings rely on comparing the digitized vsns to the corresponding thresholds programmed using pmbus commands vout_ov_warn_limit , vout _uv_fault _limit and vout_uv_warn_limit respectively (or the corresponding registers in the case of ir38165 and ir38365) . power good output the vsns voltage is an input to the window comparator with programmable thresholds. the pgood signal is high whenever vsns vo ltage is within the pgood comparator window thresholds. the pgood pin is open drain and it needs to be externally pulled high. high state indicates that output is in regulation. for the ir38163 and ir38363, th e power good thresholds may be changed through the power_good_on and power_good_off commands, which set the rising and falling pgood thresholds respectively. for the ir38165 and ir38365, which lack pmbus, the thresholds may be programmed using the corresponding mtp registers. however, when no resistive divider is used, such as for output voltages lower than 2.555v, the power good thresholds must be programmed to within 630 mv of the output voltage, otherwise, the effective power good threshold changes from an absolute threshold to one that tracks the ou tput voltage with a 630 mv offset. by default, the pgood signal will assert as soon as the vsns signal enters the regulation window. in digital mode, this delay is programmable from 0 to 10ms with a 1 ms resolution, using the mfr_tpgdly command. the threshold is set differently in svid mode. in this mode, the thresholds set by the power_good_on and power_good_off commands (or the corresponding registers) are ignored. power good is asserted when the output voltage is within the tolerance band of th e boot voltage . following this, the power good signal remains ass e rted irrespective of any output voltage transitions and is de - asserted only in the event of a fault that shuts down power conversion, or, if so programmed, in the event of a command by the c pu to change the output voltage to 0 v. ir38163/363/165/365 39 rev 3.3 dec 1 5 , 2017 figure 19 : power good in pmbus mode figure 20 : power good in svid mode , vboot >0 v 0 0 0 fault dac pgd vsns power good upper threshold power good lower threshold 160 us 0 reference dac 0 0 0 fault dac pgd vsns vboot +/ - tob 0 reference dac ir38163/363/165/365 40 rev 3.3 dec 1 5 , 2017 over - voltage prote ction (ovp) over - voltage protection is achieved by comparing sense pin voltage vsns to a configurable overvoltage threshold. t he ovp threshold may be reprogrammed to within 655 mv of the output voltage (for o utput voltages lower than 2.555 v, without any resistive divider on the fb pin), using the vout_ov_fault_limit pmbus command or the corresponding registers (for ir38363 and ir38365) . for an ovp threshold programmed to be more than 655 mv greater than the output voltage, the effective ov threshold cease s to be an absolute value and instead tracks the output voltage with a 655 mv offset. when vsns exceeds the over voltage threshold, an over voltage trip signal asser ts after 200ns (typ.) delay. the default response is that t he hig h side drive signal hdrv i s latched off immediately and pgood flags are set low. the low side drive signal is kept on until the vsns voltage drops below the threshold. hdrv remains latched off until a reset is performed by cycling either vcc or enable or the operation command. the device allows the user to reconfigure this response by the use of the vout_ov_fault_response pmbus command. in addition to the default response described above, this command can be used to configure the device such that vout overvoltage faults are ignored and the converter remains enabled. (however, they will still be flagged in the status_registers and by salert ). for further details on the corresponding pmbus commands related to ovp, please refer to the un0075 ir3816x_ir3826x_ir3836x_ pm bus commandset user note. vsns voltage is set by an external resistive voltage divider connected to the output. this divider ratio must match the divider used on the feedback pin or on the rs+ pin. it should be noted that the overvoltage threshold applies in pmbus mode as well as svid mode. figure 21 : timing diagram for ovp in non - tracking mode h d r v 0 0 0 l d r v v o u t d a c 1 + o v _ o f f s e t _ d a c c o m p 0 0 p g o o d d a c 1 2 0 0 n s h y s t e r e s i s 2 0 0 n s ir38163/363/165/365 41 rev 3.3 dec 1 5 , 2017 minimum on time cons iderations the minimum on time is the shortest amount of time for ctrl fet to b e reliably turned on. this is a very critical parameter for low duty cycle, high frequency applications. in the conventional approach, when the error amplifier output is near the bottom of the ramp waveform with which it is compared to generate the pwm output, propagation delays can be high enough to cause pulse skipping, and hence limit the minimum pulse width that can be realized. moreover, in the conventional approach, the bottom of the ramp often presents a high gain region to the error amplifier output, making the modulator more susceptible to noise and requiring the use of lower control loop bandwidth to prevent noise, jitter and pulse skipping. i nfineon has developed a proprietary sc heme to improve and enhance the minimum pulse width which minimizes these delays and hence, allows stable operation with pulse - widths as small as 35ns. at the same time, this scheme also has greater noise immunity, thus allowing stable, jitter free operati on down to very low pulse widths even with a high control loop bandwidth, thus reducing the required output capacitance. any design or application using these devices must ensure operation with a pulse width that is h igher than the minimum on - time and at l east 50 ns of on - time is recommended in the application. this is necessary for the circuit to operate without jitter and pulse - skipping, which can cause high inductor current ripple and high output voltage ripple. ( 2 ) in any application that uses these devices , the following condition must be satisfied: ( 3 ) ( 4 ) ( 5 ) the minimum output voltage is limited by the reference voltage and hence v out(min) = 0. 5 v. therefore, for v out(min) = 0. 5 v, ( 6 ) s in out s on f pv v f d t ? ? ? on on t t ? (min) s in out on f pv v t ? ? (min) (min) on out s in t v f pv ? ? ? (min) on out s in t v f pv ? ? ? s ns v f pv s in v/ 10 50 5 . 0 ? ? ? ? ir38163/363/165/365 42 rev 3.3 dec 1 5 , 2017 therefore, at the maximum recommended input voltage 16 v and minimum output voltage, the converter should be designed at a switching frequency that does not exceed 625 khz. c onversely, for operation at the maximum recom mended operating frequency ( 1.5 mhz) an d minimum output voltage (0.5v), t he input voltage (pvin) should not exceed 6.7 v , otherwise pulse skipping may happen. maximum duty ratio a n upper limit on the operating duty ratio is imposed by the larger of a) a fixed off time (dominant at high switc hing frequencies) b) blanking provided by the pwmset or clock pulse, which has a pulse width that is 1/8 of the switching period. the latter mechanism is dominant at lower switching frequencies (typically below 1.25 mhz ) . this upper limit ensures that the sync fet turns on for a long enough duration to allow recharging the bootstrap capacitor and also allow s current sensing. fi gure 22 shows a plot of the maximum duty ratio vs. the switching frequency with built in input volta ge feed forward mechanism . fi gure 22 : maximum duty cycle vs. switching frequency bootstrap capacitor to drive the control fet, it is necessary to supply a gate voltage at least 4v greater than the voltage at the sw pin, which is connected to the source of the control fet. this is achieved by using a bootstrap configuration, which comprises the internal bootstrap diode and an external bootstrap capacitor (c1). typically a 0.1uf capacitor is used. a layout placement for a 0 ohm resistor in series with the capacitor is also recommended. for applications where pvin>14v, a 1 ohm resistor is required. the operation of the circuit is as follows: when the sync fet is turned on, the capacitor node connected to sw is pulled down to gro und. the capacitor charges towards v cc through the internal bootstrap diode ( figure 23 ), which has a forward voltage drop v d . the voltage v c across the bootstrap capacitor c1 is approximately given as: ( 7 ) when the control fet turns on in the next cycle, the capacitor node connected to sw rises to the bus voltage pvin. however, if the value of c1 is appropriately chosen, the voltage vc across c1 remains approximately unchanged and the voltage at the boot pin becomes: ( 8 ) d cc c v v v ? ? boot in cc d v pv v v ? ? ? ir38163/363/165/365 43 rev 3.3 dec 1 5 , 2017 figure 23 : bootstrap circuit to generate high side drive voltage intel svid interface the se devices implement a fully compliant intel ? vr 13, and vr 12.5 serial vid (svid) interface. this is a three - wire interface between an intel processor and a vr that consists of clock, data and alert# signals. this family of devices implements all the required svid registers and commands per intel specifications. for the selected intel mode, these devices also implement most of the optional commands and registers with very few exceptions. the default svid address es of the se devices are as below. this address can be re - programmed in mtp. all call support all call for these devices can be configured in following ways: ? 0e and 0f. ? 0e only. ? 0f only. ? no all call the devices can be configured to be used as vr for cpu which is all call 0f or memory which is all call 0e. device default svid address ir38163, ir38165 02 ir38363, ir38365 03 l vc c 1 pv in v cc sw + - boot pgnd + v d - ir 38163 cvin ir38163/363/165/365 44 rev 3.3 dec 1 5 , 2017 vr 12.5 operation vr 12.5 mode is selectable via mtp bit. the boot voltage in vr 12.5 is also selectable and can be taken from the boot registers . the resolution is programmable via mtp bit to 10 mv to be compatible to vr12.5 mode. vr 13 operation vr 13 mode is selectable via mtp bit. the boot voltage in vr 13 mode is co nfigured in the boot register. the resolution is programmable via mtp bit to 5 mv to be compatible to vr13 mode. set work point this family of devices supports svid set wp command to set vid voltage for all rails through all call address. when processor asserts a set wp command, all the rails of the vr settle to the corresponding new set voltage encoded in wp registers. slew rate and power state of all the rails are identical during a set work point operation. dynamic vid slew rat e the device provides the vr designer 16 fast slew rates that govern the rate of vid transitions. the slow slew rate is also programmable as a function of the fast slew rate, a nd 4 different options are available for each setting of the fast slew rate as shown below in table 5. t able 5 : s lew r ates mv/ s fast rate x 1/2 factor x 1/4 factor x 1/8 factor x 1/16 factor 10 5.0 2.50 1.25 0.0625 15 7.5 3.75 1.875 0.94 20 10 5.00 2.50 1.25 25 12.5 6.25 3.125 1.56 30 15 7.5 3.75 1.88 35 17.5 8.75 4.375 2.19 40 20 10 5.0 2.5 45 22.5 11.25 5.625 2.81 50 25 12.5 6.25 3.125 55 27.5 13.75 6.875 3.4375 60 30 15 7.5 3.75 65 32.5 16.25 8.125 4.0625 70 35 17.5 8.75 4.375 80 40 20 10 5 ir38163/363/165/365 45 rev 3.3 dec 1 5 , 2017 loop compensation feedback loop compensation is achieved using standard type iii techniques and the compensation values can be easily calculated using infineons design tool. the design tool can also be used to predict the control bandwidth and phase margin for the loop for any set of user defined compensation component values. for a theoretical understanding of the calculations used, please refer to infineons application note an - 1162 compensator design procedure for buck converter with voltage - mode error - amplifier. dynamic vid compensa tion this family of devices uses an analog control scheme with voltage mode control. in this scheme, the compensator acts on the vout signal and not just on the error si gnal. for load and line transients, with a steady and unchanging reference voltage, this has the same dynamic characteristics as for a compensator that acts on only the error signal. however, for reference voltage changes, as in the case of dynamic vid, th e dynamics are altered. a proprietary and patented dynamic vid compensation scheme allows the dynamic vid response to be tuned optimally to the feedback compensat or values. once properly optimized , the output voltage will follow the dac more closely during a positive dynamic vid, and provide better dynamic vid alert timing, as required by intel ? processors. infineons design tool will allow the user to quickly and conveniently calculate the dynamic vid compensation parameters for optimal dynamic vid respons e. ir38163/363/165/365 46 rev 3.3 dec 1 5 , 2017 layout recommendatio ns the layout is very important when designing high frequency switching converters. layout will affect noise pickup and can cause a good design to perform with less than expected results. make the connections for the power componen ts in the top layer with wide, copper filled areas or polygons. in general, it is desirable to make proper use of power planes and polygons for power distribution and heat dissipation. the input capacitors, inductor, output capacitors and the device should be as close to each other as possible. this helps to reduce the emi radiated by the power traces due to the high switching currents through them. place the input capacitor directly at the pvin pin of ir38x6x. power vias should be at least 20/10 mil and a good rule of thumb is to design at 2a/via. the feedback part of the system should be kept away from the inductor and other noise sources. the critical bypass components such as capacitors for vin, vcc and 1.8v should be close to their respective pins. it is important to place the feedback components including feedback resistors and compensation components close to fb and comp pins. in a multilayer pcb use one layer as a power ground plane and have a control circ uit ground (analog ground), to which all signals are referenced. the goal is to localize the high current path to a separate loop that does not interfere with the more sensitive analog control functions. these two grounds must be connected together on the pc board layout at a single point. it is recommended to place all the compensation parts over the analog ground plane in top layer. the power qfn is a thermally enhanced package. based on thermal performance it is recommended to use at least a 6 - layer pcb . to effectively remove heat from the device the exposed pad should be connected to the ground plane using vias. ir38163/165/363/365 devices have 3 pins, scl, sda and salert# that are used for i2c/pmbus communication. it is recommended that the traces us ed for these communication lines be at least 10 mils wide with spacing between the scl and sda traces that is at least 2 - 3 times the trace width. ir38163/363/165/365 47 rev 3.3 dec 1 5 , 2017 i2c protocols all registers may be accessed using either i2c or pmbus protocols. i2c allows the use of a simple format whereas pmbus provides error checking capability. figure 24 shows the i2c format employed by the ic. figure 24 : i2c format smbus/pmbus protocol s to access irs configuration and monitoring registers, 4 different protocols are required: ? the smbus read/write byte/word protocol with/without pec (for status and monitoring) ? the smbus send byte protocol with/without pec (for clear_faults only) ? the smbus block read protocol for accessing model and revision information ? the smbus process call (for accessing configuration registers) in addition, the ic supports: ? alert response address (ara) ? bus timeout ? group command for writing to many vrs within one command a a s slave address w register address data byte 1 7 1 8 s 1 7 w 1 a p 8 1 1 1 1 8 write read 1 s 1 7 r 1 8 n p 1 1 s : start condition a : acknowledge ( 0 ' ) n : not acknowledge ( 1 ' ) sr : repeated start condition p : stop condition r : read ( 1 ' ) w : write ( 0 ' ) pec : packet error checking *: present if pec is enabled : master to slave : slave to master a a register address a slave address slave address data byte ir38163/363/165/365 48 rev 3.3 dec 1 5 , 2017 figure 25 : smbus write byte/word figure 26 : smbus read byte/word figure 27 : smbus send byte figure 28 : smbus block read with byte count=1 s s l a v e a d d r e s s w c o m m a n d c o d e d a t a b y t e 1 7 1 8 s 1 s l a v e a d d r e s s 7 w 1 a a a a p 8 1 1 1 1 c o m m a n d c o d e d a t a b y t e h i g h 8 a 8 1 d a t a b y t e l o w a 8 1 p e c * 8 1 a * a p 1 1 p e c * 8 1 a * b y t e w o r d s : s t a r t c o n d i t i o n a : a c k n o w l e d g e ( 0 ' ) n : n o t a c k n o w l e d g e ( 1 ' ) s r : r e p e a t e d s t a r t c o n d i t i o n p : s t o p c o n d i t i o n r : r e a d ( 1 ' ) w : w r i t e ( 0 ' ) p e c : p a c k e t e r r o r c h e c k i n g * : p r e s e n t i f p e c i s e n a b l e d : m a s t e r t o s l a v e : s l a v e t o m a s t e r p s r 7 r 8 d a t a b y t e s s l a v e a d d r e s s w c o m m a n d c o d e 1 7 1 8 a n a a 1 1 1 1 1 1 1 p n d a t a b y t e l o w 1 1 d a t a b y t e h i g h 8 s r 7 r s w 1 7 1 8 a a a 1 1 1 1 1 8 p e c * 8 a * 1 1 p e c * 8 a * 1 b y t e w o r d s l a v e a d d r e s s s l a v e a d d r e s s c o m m a n d c o d e s l a v e a d d r e s s a p p e c * 8 s s l a v e a d d r e s s w c o m m a n d c o d e 1 7 1 8 a a * a 1 1 1 1 a 1 s s l a v e a d d r e s s w c o m m a n d c o d e 1 7 1 8 a a 1 1 b y t e c o u n t = 1 d a t a b y t e 8 s r r 1 7 1 a 1 8 p n 1 1 a * 1 p e c * 8 s l a v e a d d r e s s ir38163/363/165/365 49 rev 3.3 dec 1 5 , 2017 figure 29 : mfr specific command to write a n internal r egister figure 30 : smbus custom process call to read a n internal r egister figure 31 : group command a 1 a h i g h d a t a b y t e a a a w a l o w d a t a b y t e a a w a a a a 8 8 s w 1 7 1 8 1 1 1 1 8 p e c 1 * 1 h i g h d a t a b y t e 1 o r m o r e b y t e s 8 8 s r c o m m a n d c o d e 2 1 7 1 8 1 1 1 1 a 8 p e c 2 * 1 a * 1 o r m o r e b y t e s 8 8 s r 1 7 1 8 1 1 1 1 8 p e c n * 1 o r m o r e b y t e s p 1 a * l o w d a t a b y t e s l a v e a d d r e s s 1 s l a v e a d d r e s s 2 c o m m a n d c o d e 1 h i g h d a t a b y t e s l a v e a d d r e s s n c o m m a n d c o d e n l o w d a t a b y t e s p m b u s a d d r e s s w c o m m a n d d 1 h r e g i s t e r a d d r e s s d a t a b y t e a a a a p p e c * a s p m b u s a d d r e s s w c o m m a n d d 0 h r e g i s t e r a d d r e s s p s r p m b u s a d d r e s s r a a a a d a t a b y t e a p e c * n a d d r e s s + 1 d a t a b y t e a * . . . ir38163/363/165/365 50 rev 3.3 dec 1 5 , 2017 pcb pads and compone nt ir38163/363/165/365 51 rev 3.3 dec 1 5 , 2017 pcb copper and solde r resist (pad sizes) pcb copper and solde r resist (pad spacin g) ir38163/363/165/365 52 rev 3.3 dec 1 5 , 2017 solder paste stencil (pad sizes) solder paste stencil (pad spacing) ir38163/363/165/365 53 rev 3.3 dec 1 5 , 2017 marking information ir38163/363/165/365 54 rev 3.3 dec 1 5 , 2017 package information ir38163/363/165/365 55 rev 3.3 dec 1 5 , 2017 ir38163/363/165/365 56 rev 3.3 dec 1 5 , 2017 e nvironmental qualifi cations qualification level industrial moisture sensitivity level 5mm x 7mm pqfn msl 2 260c esd machine model (jesd22 - a115a) jedec class a human body model (jesd22 - a114f) jedec class 1c charged device model (jesd22 - c101f) jedec class 3 rohs compliant yes (with exemption 7a) ? qualification standards can be found at international rectifier web site: http://www.irf.com ir38163/363/165/365 57 rev 3.3 dec 1 5 , 2017 supported pmbus comm ands comma nd code command name smbus transactio n no. of bytes range resoluti on default value description 01h operation r/w byte 1 enables or disables the device and controls margining 02h on_off_config r/w byte 1 configures the combination of enable pin input and serial bus commands needed to turn the unit on and off. 03h clear_faults send byte 0 clear contents of fault registers 10h write_protect r/w byte 1 used to control writing to the pmbus device. the intent of this command is to provide protection against accidental changes. 15h store_user_all send byte 0 burns the user section registers into otp memory 16h restore_user_all send byte 0 copies the otp registers into user memory 19h capability read byte 1 returns 1011 xxxx to indicate packet error checking is supported, m aximum bus speed is 400khz and smbalert# is supported. 1bh smbalert_mask write word/block read process call 2 may be used to prevent a warning or fault condition from asserting the smbalert# signal. 21h vout_command 1 6 r/w word 2 0 - 2.555v/v s 5mv /v s 1 v causes the device to set its output voltage to the commanded value . v s = vout_scale_loop 22h vout_trim 1 6 r/w word 2 - 128 - +128v 0v available to the device user to trim the output voltage 24h vout_max 1 6 r/w word 2 2 v sets an upper limit on the output voltage the unit can command regardless of any other commands or combinations. 25h vout_margin_high 1 6 r/w word 2 0 - 2.555v/v s 5mv /v s sets the margin high voltage when commanded by operation v s = vout_scale_loop 26h vout_margin_low 1 6 r/w word 2 0 - 2.555v/v s 5mv /v s sets the margin low voltage when commanded by operation v l = vout_scale_loop 27h vout_transition_rate 11 r/w word 2 0 - 63.9mv/us 0.0625m v/us 0.0625m v/us sets the rate in mv/s at which the output should change voltage. exponent 0 to - 4 allowed. 29h vout_scale_loop 1 1 r/w word 2 0.125 - 1 1 compensates for external resistor divider in feedback path and in the sense path . values 1, 0.5, 0.25, 0.125 allowed. exponent - 3 allowed. 33h frequency_switch 11 r/w word 2 166 - 1500khz 978khz sets the switch ing frequency, in khz . exponent 0 to 1 allowed. 35h vin_on 11 r/w word 2 0 - 16.5v 0.5v 8 v sets the value of the input voltage, in volts, at which the unit should start power conversion. exponent - 1 allowed. 36h vin_off 11 r/w word 2 0 - 16v 0.5v 7.0 v sets the value of the input voltage, in volts, at which the unit, once operation has started, should stop power conversion. exponent - 1 allowed. 39h iout_cal_offset 11 r/w word 2 - 128a - +127.5a 0. 2 5a 0a used to null out any offsets in the output current sensing circuit. exponent - 2 allowed. 40h vout_ov_fault_limit 1 6 r/w word 2 (25 - 655mv)/v s 10mv/v s 2.102 v sets the value of the output voltage measured at the sense pin that causes an output overvoltage fault. v s = vout_scale_loop 41h vout_ov_fault_respons e r/w byte 1 ignore/shu tdown shutdow n instructs the device on what action to take in response to an output overvoltage fault. 42h vout_ov_warn_limit 1 6 r/w word 2 3.9mv 1.902 v sets the value of the output voltage at the sense pin that causes an output voltage high ir38163/363/165/365 58 rev 3.3 dec 1 5 , 2017 comma nd code command name smbus transactio n no. of bytes range resoluti on default value description warning. 43h vout_uv_warn_limit 1 6 r/w word 2 3.9mv 0.902 v sets the value of the output voltage at the sense pin that causes an output voltage low warning. 44h vout_uv_fault_limit 1 6 r/w word 2 3.9mv 0.898 v sets the value of the output voltage at the sense pin that causes an output undervoltage fault. 45h vout_uv_fault_respons e r/w byte 1 ignore/shu tdown ignore instructs the device on what action to take in response to an output undervoltage fault. 46h iout_oc_fault_limit 11 r/w word 2 12 - 56 a 4a 40 a , 20a sets the value of the output current, in amperes, that causes the overcurrent detector to indicat e an overcurrent fault . exponent - 1 allowed. 47h iout_oc_fault_response r/w byte 1 pulse by pulse for 8 cycles followed by hiccup, retry after 20 ms instructs the device on what action to take in response to an output overcurrent fault. 4ah iout_oc_warn_limit 11 r/w word 2 0 - 63.5a 0.5a 35a, 1 7.5 a sets the value of the output current, in amperes, that causes the overcurrent detector to indicate an overcurrent warning . exponent - 1 allowed. 4fh ot_fault_limit 11 r/w word 2 0 - 150 c 1 c 12 5 c set the temperature, in degrees celsius, of the unit at which it should indicate an overtemperature fault . exponent 0 allowed. 50h ot_fault_response r/w byte 1 ignore/shu tdown/inhi biit auto - start instructs the device on what action to take in response to an overtemperature fault. 51h ot_warn_limit 11 r/w word 2 0 - 150 c 1 c 100 c set the temperature, in degrees celsius, of the unit at which it should indicate an overtemperature warning alarm. exponent 0 allowed. 55h vin_ov_fault_limit 11 r/w word 2 6.25v - 24v 0.25v 15 v sets the value of the input voltage that causes an input overvoltage fault. exponent - 2 allowed. 56h vin_ov_fault_response r/w byte 1 ignore/shu tdown ignore instructs the device on what action to take in response to an input overvoltage fault. 58h vin_uv_warn_limit 11 r/w word 2 0 - 16v 0.5v 7 .5v sets the value of the input voltage pvin, in volts, that causes an input overvoltage fault. exponent - 1 allowed. 5eh power_good_on 16 r/w word 2 (0 - 0.63v)/v s 10mv /v s 0. 5v sets the output voltage at which an optional power_good signal should be asserted. v s =vout_scale_loop 5fh power_good_off 1 6 r/w word 2 (0 - 0.63v)/v s 10mv /v s 0. 2 5 v sets the output voltage at which an optional power_good signal should be negated. v s =vout_scale_loop 60h ton_delay 11 r/w word 2 0 - 127ms 1ms 0ms sets the time, in milliseconds, from when a start condition is received (as programmed by the on_off_config command) until the output voltage starts to rise. exponent 0 allowed. 61h ton_rise 11 r/w word 2 0 - 127ms 1ms 1 ms sets the time, in milliseconds, from when the output starts to rise until the voltage has entered the regulation band. exponent 0 allowed. 62h ton_max_fault_limit 11 r/w word 2 0 - 127ms 1ms 0 (disable d ) sets an upper limit, in milliseconds, on how long the unit can attempt to power up the output without reaching the output undervoltage fault limit . exponent 0 allowed. 63h ton_max_fault_respons e r/w byte 1 ignore/shu tdown ignore instructs the device on what action to take in response to a ton_max fault. ir38163/363/165/365 59 rev 3.3 dec 1 5 , 2017 comma nd code command name smbus transactio n no. of bytes range resoluti on default value description 64h toff_delay r/w word 2 0 - 127ms 1ms 0ms sets the time, in milliseconds, from a stop condition is received (as programmed by the on_off_config command) until the unit stops transferring energy to the output. exponent 0 allowed. 65h toff_fall r/w word 2 0 - 127ms 1ms 1 ms s ets the time, in milliseconds, in which the reference voltage ramps down to zero (if a soft off is allowed by the configuration of the on_off_config command) . exponent 0 allowed. 78h status byte read byte 1 returns 1 byte where the bit meanings are: bit <7> device busy fault bit <6> output off (due to fault or enable) bit <5> output over - voltage fault bit <4> output over - current fault bit <3> input under - voltage fault bit <2> temperature fault bit <1> communication/memory/logic fault bit <0>: none of the above 79h status word read word 2 returns 2 bytes where the low byte is the same as the status_byte data. the high byte has bit meanings are: bit <7> output high or low fault bit <6> output over - current fault bit <5> input under - voltage fault bit <4> reserved; hardcoded to 0 bit <3> output power not good bit <2:0> hardcoded to 0 7ah status_vout read byte 1 reports types of vout related faults. 7bh status_iout read byte 1 reports types of iout related faults. 7ch status_input read byte 1 reports types of input related faults. 7dh status_temperature read byte 1 returns over temperature warning and over temperature fault (otp level). does not report under temperature warning/fault. the bit meanings are: bit <7> over temperature fault bit <6> over temperature warning bit <5> under temperature warning bit <4> under temperature fault bit <3:0> reserved 7eh status_cml read byte 1 returns 1 byte where the bit meanings are: bit <7> command not supported bit <6> invalid data bit <5> pec fault bit <4> otp fault bit <3:2> reserved bit<1> other communication fault bit<0> other memory or logic fault; hardcoded to 0 88h read_vin 11 read word 2 re turns the input voltage in volts 8bh read_vout 1 6 read word 2 returns the output voltage in volts ir38163/363/165/365 60 rev 3.3 dec 1 5 , 2017 comma nd code command name smbus transactio n no. of bytes range resoluti on default value description 8ch read_iout 11 read word 2 return s the output current in amperes 8dh read_temperature 11 read word 2 returns the device temperature in degrees celcius 96h read_pout 11 read word 2 r eturns the output power in watts 98h pmbus_revision read byte 1 reports pmbus part i rev 1.1 & pmbus part ii rev 1.2(draft ) 99h mfr_id block read/write 2 ir returns 2 bytes u se d to read the manufacturers id. user can overwrite with any value. 9ah mfr_model block read/write 3 set 00 0000 if set to 0, returns a 1 byte code corresponding to ic_device_id. alternatively, user can set to any non - zero value 9bh mfr_revision block read/write 3 set 0 0000 0 if set to 0, returns a 1 byte code corresponding to ic_device_rev. alternatively, user can set to any non - zero value adh ic_device_id block read 2 used to read the type or part number of an ic. ir38 163 : 63 h ir38 165 : 64 h ir38363 : 67 h ir38365 : 68 h aeh ic_device_rev block read 1 used to read the revision of the ic d0h mfr_read_reg custom 2 manufacturer specific: read from configuration registers d1h mfr_write_reg custom 2 manufacturer specific: write to configuration & status registers d8h mfr_tpgdly r/w word 2 0 - 10ms 1ms 0ms sets the delay in ms, between the output voltage entering the regulation window and the assertion of the pgood signal . exponent 0 allowed. d9h mfr_fccm r/w byte 1 0 - 1 1 (ccm) allows the user to choose between forced continuous conduction mode and adaptive on - time operation at light load. d6h mfr_i2c_address r/w word 1 0 - 7fh 10h sets and returns the device i2c base address dbh mfr_vout_peak 1 6 read word 2 continuously records and reports the highest value of read vout. dch mfr_iout_peak 11 read word 2 continuously records and reports the highest value of read iout. ddh mfr_temperature_peak 11 read word 2 continuously records and reports the highest value of read_temperature notes 11 uses linear11 format 1 6 uses linear16 format with exponent set to - 8 ir38163/363/165/365 61 rev 3.3 dec 1 5 , 2017 revision history 0.0 9/5/2014 initial release 0.1 9/17/2014 removed references to imon, tmon, ocset and rt/sync; added config option for 3 bit vid, corrected pinout 0.2 9/17/2014 added packaging info 0.3 9/25/2015 changed current rating to 30a 0.4 12/8/2014 deleted the pvid mode reference and added spec tables 0.5 4/14/2015 updated pod and package info, updated description on first page, update mfr_write_reg and mfr_read_reg description. combined all svid parts into 1 datasheet, combined 163/165/363/365 datasheets 0.6 3/18/2016 added theory of operation, updated application diagrams, updated boot to sw spec 0.7 4/22/2016 combined pod and pin tables, added more description to the pin table, updated typical apps diagrams, typo fix es 0.8 4/25/2016 changed to infineon format 0.9 5/18/2016 reduc ed vin range from 21v to 16v : rb changed from supirbuck to optimos ipol brand :rb changed max duty chart to reflect 200 khz to 2 mhz range changed min time calculation change iout_oc_fault_limit range in pmbus table added manhattan svid ids for ic_device_id added small section on dynamic vid and prefilter (called dynamic vid compensation just like the mp parts) truncated vboot table at 0.4v removed min max spec for rdson 1.0 9/1/2016 corrected typos, added typical operating curves from ate data, limited acceptable oc response types. 1.1 10/27/2016 updated pvin telemetry spec, updated ioc fault limits in spec table and description, added lvt thresholds for pmbus and pulldown resistance for data and alert, fsw max=1.5 mhz , corrected defaults in pmbus table, updated qual table , added compliance info for for vr12, vr13 and svid 1.2 11/3/2016 added note discouraging aot use, added imon curves , corrected fsw range typos, changed e sd ratings, changed from concept to preliminary 1.3 12/9/2016 added efficiency curves, added ocp char curves and ds limits, changed ldo test condition 1.4 1/13/2017 corrected typos and changed first page to preliminary 3.0 3/9/2017 added marking diagrams 3.1 3/20/2017 changed 1.8v ldo regulation current to 1 ma, added a note on bootstrap circuit and layout recommendations , stencil drawings updated 3.2 5/8/2017 added requirement of 1 ohm series resistor for pvin>14v 3.3 12/12 /2017 fixed ocp description and diagram plus updated other functionality sections . added recommendation to use 10uf bypass capacitor at p1v8 pin. updated the default values on the pmbus section . updat ed application diagrams. ir38163/363/165/365 62 rev 3.3 dec 1 5 , 2017 published by infineon technologies ag 81726 mnchen, germany ? infineon technologies ag 2015 all rights reserved. important notice the information given in this document shall in no event be regarded as a guarantee of conditions or characteristics (beschaffenheitsgarantie). with respect to any examples, hints or any typical values stated herein and/or any information regarding the application of the product , infineon technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non - infringement of intellectual property rights of any third party. in addition , any information given in this document is subject to customer s com pliance with its obligations stated in this document and any applicable legal requirements, norms and standards concerning customers products and any use of the product of infineon technologies in customers applications. the data contained in this docu ment is exclusively intended for technically trained staff. it is the responsibility of customers technical departments to evaluate the suitability of the product for the intended application and the completeness of the product information given in this d ocument with respect to such application. for further information on the product, technology, delivery terms and conditions and prices please contact your nearest infineon technologies o ffice ( www.infineon.com ). warnings due to technical requirements products may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies o ffice. except as otherwise explicitly approved by infineon technologies in a wri tten document signed by authorized representatives of infineon technologies, infineon technologies products may not be used in any applications where a failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury. |
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